ASE Pushes Panel-Level Packaging Automated Line, Targeting Mass Production in First Half of 2027
ASE Semiconductor announced on the 27th the development of a 310mm x 310mm panel-level packaging (PLP) automated line, with mass production expected in the first half of 2027. This technology aims to meet the demand for advanced packaging for AI accelerators and HPC components by using rectangular panels to improve material utilization and production efficiency.
📋 Article Processing Timeline
- 📰 Published: May 27, 2026 at 18:35
- 🔍 Collected: May 31, 2026 at 23:45 (101h 10m after Published)
- 🤖 AI Analyzed: June 2, 2026 at 00:58 (25h 12m after Collected)
(Central News Agency, reporter Zhong Rongfeng, Taipei, 27th) Semiconductor packaging and testing giant ASE Semiconductor announced today that it has developed a 310mm x 310mm panel-level packaging (PLP) automated line. The new panel packaging line is expected to enter mass production in the first half of 2027 to meet the demand for advanced packaging for artificial intelligence (AI) accelerators and high-performance computing (HPC) components.
ASE stated in a press release that the panel-level packaging automated line supports the 310mm x 310mm specification and is compatible with its own FOCoS (Fan-Out Chip on Substrate) and FOCoS-Bridge (Fan-Out Chip on Substrate-Bridge) advanced packaging platforms. By converting from traditional circular wafers to rectangular panels, it can significantly increase the usable area, improve the number of chips that can be packaged per unit, and enhance material utilization.
ASE pointed out that building the panel-level packaging automated line can achieve high-bandwidth, low-latency interconnection between chiplets, application-specific integrated circuits (ASIC), and high-bandwidth memory (HBM), thereby improving overall performance.
ASE analyzed that panel-level packaging is a long-term challenge for the industry, including issues such as the continuous increase in interposer size and the decline in wafer-level packaging efficiency. The larger the panel specification, the higher the throughput it can support, which shortens the overall production cycle and integrates increasingly complex multi-chip architectures. (Editor: Zhang Liangzhi)
ASE stated in a press release that the panel-level packaging automated line supports the 310mm x 310mm specification and is compatible with its own FOCoS (Fan-Out Chip on Substrate) and FOCoS-Bridge (Fan-Out Chip on Substrate-Bridge) advanced packaging platforms. By converting from traditional circular wafers to rectangular panels, it can significantly increase the usable area, improve the number of chips that can be packaged per unit, and enhance material utilization.
ASE pointed out that building the panel-level packaging automated line can achieve high-bandwidth, low-latency interconnection between chiplets, application-specific integrated circuits (ASIC), and high-bandwidth memory (HBM), thereby improving overall performance.
ASE analyzed that panel-level packaging is a long-term challenge for the industry, including issues such as the continuous increase in interposer size and the decline in wafer-level packaging efficiency. The larger the panel specification, the higher the throughput it can support, which shortens the overall production cycle and integrates increasingly complex multi-chip architectures. (Editor: Zhang Liangzhi)
FAQ
What are the benefits of ASE's new packaging technology?
Using rectangular panels significantly improves material utilization and production efficiency.