Unraveling the Temperature Dependence of Silicon Qubits: New Insights into Noise Mechanisms Improving Gate Fidelity

【Research Summary and Highlights】

- The generation mechanism of noise that reduces the performance of silicon qubits was analyzed using theoretical models and statistical simulations.
- Conditions for improving the accuracy (fidelity) of quantum gate operations when operated at higher than usual temperatures (approx. 200 mK) were identified through simulation.
- It was suggested that "electron transitions" are a more plausible cause of noise than "atomic movement."
- These research results provide guidelines for future large-scale, high-density silicon quantum computer design, such as charge trap control at interfaces.

【Research Overview】

A joint research group from the Tokyo University of Science and the National Institute of Advanced Industrial Science and Technology (AIST) reproduced and analyzed the temperature-dependent shifts in qubit frequency observed in silicon spin qubits and the improvement in gate fidelity during higher-temperature operation within the cryogenic range, using statistical simulations based on charge noise derived from two-level fluctuators (TLFs). After systematically evaluating numerous parameter settings, they demonstrated that an exponential distribution of TLF activation energy, short minimum transition times, and steep temperature dependence are crucial for reproducing experimental results and improving fidelity. Based on this, they concluded that electron transitions are a more plausible origin for the primary source of TLFs. This research provides insights useful for future device design and trap control strategy studies.

This research was published online in the international academic journal "IEEE ACCESS" on May 4, 2026.

【Research Background】

Quantum computers are highly anticipated as a next-generation technology. Silicon qubits, in particular, are one of the most promising methods for scaling up due to their compatibility with existing semiconductor manufacturing technology. However, performance degradation due to thermal fluctuations and minute noise remains a significant challenge. Specifically, changes in the resonant frequency (Larmor frequency) of the qubit during operation cause shifts in microwave control resonant conditions, reducing the accuracy (fidelity) of gate operations. Recent experiments have reported a seemingly contradictory phenomenon where performance improves when operated at a slightly higher temperature (approx. 200 mK) than the usual cryogenic temperature (approx. 20 mK), but the mechanism behind this was unknown.

【Details of Research Results】

The research group focused on numerous TLFs assumed to exist at the semiconductor/oxide interface near Si/SiGe quantum dots and examined their temperature-dependent dynamics in detail through numerical simulation. They built a model including quantum dots and external magnetic field gradients, varying diverse parameters such as TLF spatial arrangement, activation energy distribution, and minimum transition time, to explore conditions that could reproduce the "non-monotonic temperature dependence of the Larmor frequency" and "gate fidelity improvement at high temperatures" reported in experiments. They generated and statistically analyzed 5,000 TLF distributions for each of the 108 parameter settings.

The simulations showed that the experimental results were best reproduced when the TLF activation energy followed an exponential distribution and the transition time response to temperature changes was steep. Given these trends and the small activation energy of a few meV, they concluded that electron transitions between the conduction band and shallow trap states are a more potent origin than mechanisms involving large-scale atomic movement. Therefore, control of the semiconductor/oxide interface state and process improvement are key means for stabilizing quantum gate frequencies and achieving high-fidelity operation in future large-scale quantum computers.

Moving forward, the group will conduct experimental verification using interface trap state control, such as bias cooling, apply the findings to device design and process improvement, and extend the research to large-scale simulations reflecting more realistic spatial and energy distributions.