2nm, A14 Takes Over! TSMC Unveils Next-Gen Process Roadmap, High NA EUV Adoption Based on Three Conditions

While the global semiconductor industry remains focused on 2nm mass production, TSMC (2330) has already begun planning its next-generation technology roadmap. Chairman and CEO C.C. Wei stated during the earnings call that the 2nm process has smoothly entered mass production, and the A14 process will begin risk production in 2027 and volume production in 2028. Regarding the much-anticipated High NA EUV (High Numerical Aperture Extreme Ultraviolet) equipment, TSMC is not rushing to be the first adopter but will decide the timing based on three conditions: technology maturity, volume production capability, and cost-effectiveness. Wei used the analogy of "buying milk at 7-ELEVEN" to explain that advanced process competition is not something that can be switched overnight, but rather a multi-year process of technical collaboration and trust-building.

The 2nm (N2) process has officially entered mass production and began contributing to revenue in Q2, accounting for approximately 3% of wafer revenue. TSMC stated that the 2nm ramp-up speed is better than the initial phase of 3nm, and customer adoption is progressing smoothly. It is expected that within the next five years, the number of new chip designs (new tape-outs) will exceed that of 3nm and 5nm at the same stage.

However, the rapid expansion of 2nm production will bring short-term pressure on profitability. CFO Lora Ho indicated that since 2nm is still in the capacity ramp-up phase, it is expected to dilute gross margin by about 3 to 4 percentage points in the second half; additionally, higher initial operating costs at overseas new fabs will bring about a 2 to 3 percentage point impact. However, as demand continues to grow, production efficiency improves, and cross-generational process capacity is optimized, these impacts are expected to be gradually offset.

Regarding when 2nm will truly reflect in revenue, TSMC explained that it typically takes about 6 to 8 months from wafer start to customer product launch. Therefore, even though 2nm has started large-scale wafer input, the revenue contribution will gradually emerge in line with customer product launch schedules, rather than being reflected all at once.

In addition to 2nm, TSMC also updated its next-generation A14 process roadmap. According to the company's plan, A14 is expected to begin risk production in 2027 and enter volume production in 2028. Compared to N2, A14 can deliver 10% to 15% higher computing performance at the same power consumption, or reduce power consumption by 25% to 30% at the same performance level, with logic density improving by approximately 20%. It will continue to target high-end chip applications in AI, high-performance computing, and smartphones.

Wei stated that TSMC is also planning post-A14 derivative processes. A13 will use Optical Shrink technology to reduce chip area by about 6% compared to A14; A12 will introduce Super Power Rail (SPR) technology to further enhance power delivery efficiency. Both processes are expected to enter volume production in 2029, expanding the A14 family to meet diverse customer needs.

Another highly anticipated topic at the earnings call was the timeline for adopting ASML's High NA EUV equipment. Facing market competition to adopt High NA EUV, Wei did not provide a clear timeline but reiterated TSMC's consistent pragmatic strategy.

TSMC further stated that its evaluation of new equipment adoption is not based on whether the equipment is "latest," but must meet three conditions: first, the technology itself must be sufficiently mature; second, it must support high-volume production with high yield; third, and most importantly, it must offer reasonable cost-effectiveness (cost-effective) and truly create value for customers.

TSMC emphasized that even the most advanced technology will not be adopted if it cannot balance cost and volume production capability. Therefore, while High NA EUV will undoubtedly be an important technological direction in the future, the actual adoption timing will be comprehensively evaluated based on product maturity, customer demand, and economic benefits, rather than simply pursuing being the "first to adopt."

On the topic of intensifying global semiconductor competition and governments actively subsidizing foundry construction, Wei used a relatable everyday analogy to explain the difficulty of establishing competitive advantage in advanced processes.

"Many people think switching foundries is easy, but it's not like buying milk at 7-ELEVEN—you can't switch suppliers overnight," said Wei. He explained that customers typically require four to five years or more to understand a new process, complete chip design, verification, trial production, and finally mass production—a long-term collaborative effort. It's impossible to change partnerships quickly just because competitors increase capacity or governments offer subsidies.

TSMC emphasized that the true key to advanced process competition is not who acquires the latest equipment first, but who can integrate equipment, process technology, yield, cost control, and customer design services into a scalable mass production capability. This is also the key reason TSMC has maintained technological leadership for many years.

From the official mass production of 2nm, to the sequential rollout of A14, A13, and A12 generations, to the cautious planning of High NA EUV, the message from TSMC's earnings call is clear: the company is not pursuing being the first to adopt every new tool, but rather building a long-term manufacturing platform that balances technological leadership, production efficiency, and economic benefits, and through continuous innovation, solidifying its competitive advantage in advanced processes for the next decade.