OKI Establishes 180-Layer, 15mm-Thick PCB Technology for Next-Gen AI Semiconductor Testing Equipment
OKI Circuit Technology has successfully developed a 180-layer, 15mm-thick PCB for AI chip testing (HBM), breaking the previous industry limit of 124 layers. Mass production is targeted for October 2026.
📋 Article Processing Timeline
- 📰 Published: April 27, 2026 at 21:02
- 🔍 Collected: April 27, 2026 at 12:31
- 🤖 AI Analyzed: April 28, 2026 at 02:39 (14h 8m after Collected)
OKI Circuit Technology (OTC), the OKI Group's printed circuit board (PCB) business company, has successfully developed design and production technology for a 180-layer, 15mm-thick PCB for wafer testing equipment used for High Bandwidth Memory (HBM) installed in AI semiconductors. This represents an approximate 45% increase in layer count and a doubling of thickness compared to conventional 124-layer, 7.6mm-thick boards. OTC will proceed with establishing mass production technology and installing equipment at its Joetsu Plant (Joetsu City, Niigata Prefecture), which possesses high design and production technical capabilities for high-multilayer, high-definition, and large-scale PCBs, with the aim of starting mass production shipments in October 2026.
Latest AI semiconductors not only handle a massive number of signals but also have an increasing number of chips per wafer due to process miniaturization. Consequently, PCBs for testing equipment require higher density (narrower pitch) and an increased number of layers. However, increasing thickness makes it harder to control characteristic impedance of vias, degrades power performance due to via penetration through power layers, and faces drill technology constraints for processing long, thin vias. Previously, the upper limit for a single ultra-high multilayer PCB was 124 layers and a thickness of 7.6mm. Traditional structures reached their limits in meeting future high-speed, high-frequency, and high-density data transfer needs.
To address this, OTC developed 'Sintering paste for via bonding technology,' which creates ultra-high multilayer PCBs by stacking and connecting multiple multilayer PCBs (bonding surface vias to surface vias), alongside 'Ultra-thick PCB manufacturing technology' capable of handling thicknesses up to 15mm. By combining these, OTC established a unique PCB design and production technology that realizes 180 layers and a 15mm thickness by bonding three 60-layer PCBs. Since each multilayer PCB can address challenges in via characteristic control, signal quality, and power performance using established technologies before being stacked, it is possible to achieve both ultra-high layer counts and high performance/quality. This new technology enables customers to meet future needs for even higher speed, frequency, and data density.
OTC developed this technology targeting sectors where future growth is expected, such as AI semiconductors, AI servers, aerospace, defense, and next-gen communications. OTC will continue to actively develop PCBs and manufacturing technologies in response to technical evolution.
OTC will introduce this technology at 'PCB East 2026' (Booth No. 313), held at the DCU Convention Center in Massachusetts, USA, from April 28 to May 1, 2026.
Note 1: HBM (High Bandwidth Memory) - Next-generation memory with multiple stacked DRAMs and a dedicated high-speed interface.
Note 2: VIA HOLE - Holes that electrically connect layers in a multilayer PCB.
Note 3: Impedance - The ratio of voltage to current in an AC circuit, representing the resistance to current flow.
Latest AI semiconductors not only handle a massive number of signals but also have an increasing number of chips per wafer due to process miniaturization. Consequently, PCBs for testing equipment require higher density (narrower pitch) and an increased number of layers. However, increasing thickness makes it harder to control characteristic impedance of vias, degrades power performance due to via penetration through power layers, and faces drill technology constraints for processing long, thin vias. Previously, the upper limit for a single ultra-high multilayer PCB was 124 layers and a thickness of 7.6mm. Traditional structures reached their limits in meeting future high-speed, high-frequency, and high-density data transfer needs.
To address this, OTC developed 'Sintering paste for via bonding technology,' which creates ultra-high multilayer PCBs by stacking and connecting multiple multilayer PCBs (bonding surface vias to surface vias), alongside 'Ultra-thick PCB manufacturing technology' capable of handling thicknesses up to 15mm. By combining these, OTC established a unique PCB design and production technology that realizes 180 layers and a 15mm thickness by bonding three 60-layer PCBs. Since each multilayer PCB can address challenges in via characteristic control, signal quality, and power performance using established technologies before being stacked, it is possible to achieve both ultra-high layer counts and high performance/quality. This new technology enables customers to meet future needs for even higher speed, frequency, and data density.
OTC developed this technology targeting sectors where future growth is expected, such as AI semiconductors, AI servers, aerospace, defense, and next-gen communications. OTC will continue to actively develop PCBs and manufacturing technologies in response to technical evolution.
OTC will introduce this technology at 'PCB East 2026' (Booth No. 313), held at the DCU Convention Center in Massachusetts, USA, from April 28 to May 1, 2026.
Note 1: HBM (High Bandwidth Memory) - Next-generation memory with multiple stacked DRAMs and a dedicated high-speed interface.
Note 2: VIA HOLE - Holes that electrically connect layers in a multilayer PCB.
Note 3: Impedance - The ratio of voltage to current in an AC circuit, representing the resistance to current flow.