GUC Announces 12Gbps HBM4 PHY and Controller Using 3nm Process
GUC has successfully demonstrated the industry's first 12Gbps HBM4 IP platform on TSMC's 3nm process. Delivering 2.5x the bandwidth of HBM3E, it provides comprehensive support for next-generation AI and HPC semiconductors.
📋 Article Processing Timeline
- 📰 Published: April 23, 2026 at 18:00
- 🔍 Collected: April 23, 2026 at 09:31
- 🤖 AI Analyzed: April 24, 2026 at 04:14 (18h 42m after Collected)
Hsinchu, Taiwan – April 23, 2026 – GLOBAL UNICHIP CORP. (GUC), the Advanced ASIC Leader, announced today the successful demonstration of its 12Gbps HBM4 IP platform on the TSMC 3nm process at the partner exhibition area of the "TSMC 2026 North America Technology Symposium."
This platform integrates GUC's proprietary, full-featured HBM4 controller and PHY IP with partner HBM4 memory, utilizing TSMC's industry-leading CoWoS® advanced packaging technology.
GUC's previous generation HBM3E PHY and controllers have already been adopted in customers' 3nm products, achieving speeds 15% higher than specifications in mass production. JEDEC is strongly driving the HBM roadmap to enhance memory processing power and capacity, with HBM4 doubling the data bus width. Compared to HBM3E, GUC's HBM4 IP delivers substantial improvements: 2.5x the bandwidth, 1.5x the power efficiency, and 2x the area efficiency.
Furthermore, consistent with GUC's legacy HBM, GLink, and UCIe IP solutions, this new HBM4 IP integrates proteanTecs' interconnect monitoring solution. This provides high visibility during PHY testing and characterization, while also significantly improving performance and reliability during the end product's active operation.
To address the growing demand for 3DIC architectures, GUC's HBM4 PHY also supports a "face-up" configuration, enabling integration into TSMC's "SoIC face-to-face" technology. The PHY macro integrates TSV (Through-Silicon Vias) for I/O signals, power, and ground connections, and also secures TSVs for power delivery to the top die, thereby supporting the power distribution requirements of the upper logic die.
Igor Elkanovich, CTO of GUC, stated: "We are extremely proud to announce the industry's first 12Gbps HBM4 IP and to showcase these achievements to our customers at the TSMC Symposium. By combining this with our UCIe and GLink-3D IPs, we will continue to provide comprehensive 2.5D/3D IP solutions for the latest 3.5D system architectures, including TSMC 'SoIC-X on CoWoS'."
12 Gbps Eye Diagram
GUC HBM4 IP Highlights
✓ Ready for immediate deployment on TSMC N3P process: 12Gbps timing sign-off completed
✓ Next-generation HBM4E expected to be ready in Q2 2026: Supporting 16Gbps speeds
✓ Supports all TSMC CoWoS® technologies: Compatible with CoWoS-S, CoWoS-R, and CoWoS-L
✓ Adapts to advanced 3D SoIC architectures: Supports face-up stacking configurations
✓ Supports advanced interposer routing: Enables Angle-Routing via Y-direction offsets for flexible wiring
✓ Equipped with proteanTecs monitoring technology: A solution capable of real-time monitoring of inter-chiplet connectivity
Copyright © 2026 GUC. All rights reserved.
About GUC
GLOBAL UNICHIP CORP. (GUC) is the Advanced ASIC Leader, leveraging cutting-edge process and packaging technologies to provide the semiconductor industry with world-class IC implementation and SoC manufacturing services. Headquartered in Hsinchu, Taiwan, GUC has built global trust with bases in China, Europe, Japan, Korea, North America, and Vietnam. GUC is publicly traded on the Taiwan Stock Exchange (Ticker: 3443). For more information, please visit our official website (www.guc-asic.com).
This platform integrates GUC's proprietary, full-featured HBM4 controller and PHY IP with partner HBM4 memory, utilizing TSMC's industry-leading CoWoS® advanced packaging technology.
GUC's previous generation HBM3E PHY and controllers have already been adopted in customers' 3nm products, achieving speeds 15% higher than specifications in mass production. JEDEC is strongly driving the HBM roadmap to enhance memory processing power and capacity, with HBM4 doubling the data bus width. Compared to HBM3E, GUC's HBM4 IP delivers substantial improvements: 2.5x the bandwidth, 1.5x the power efficiency, and 2x the area efficiency.
Furthermore, consistent with GUC's legacy HBM, GLink, and UCIe IP solutions, this new HBM4 IP integrates proteanTecs' interconnect monitoring solution. This provides high visibility during PHY testing and characterization, while also significantly improving performance and reliability during the end product's active operation.
To address the growing demand for 3DIC architectures, GUC's HBM4 PHY also supports a "face-up" configuration, enabling integration into TSMC's "SoIC face-to-face" technology. The PHY macro integrates TSV (Through-Silicon Vias) for I/O signals, power, and ground connections, and also secures TSVs for power delivery to the top die, thereby supporting the power distribution requirements of the upper logic die.
Igor Elkanovich, CTO of GUC, stated: "We are extremely proud to announce the industry's first 12Gbps HBM4 IP and to showcase these achievements to our customers at the TSMC Symposium. By combining this with our UCIe and GLink-3D IPs, we will continue to provide comprehensive 2.5D/3D IP solutions for the latest 3.5D system architectures, including TSMC 'SoIC-X on CoWoS'."
12 Gbps Eye Diagram
GUC HBM4 IP Highlights
✓ Ready for immediate deployment on TSMC N3P process: 12Gbps timing sign-off completed
✓ Next-generation HBM4E expected to be ready in Q2 2026: Supporting 16Gbps speeds
✓ Supports all TSMC CoWoS® technologies: Compatible with CoWoS-S, CoWoS-R, and CoWoS-L
✓ Adapts to advanced 3D SoIC architectures: Supports face-up stacking configurations
✓ Supports advanced interposer routing: Enables Angle-Routing via Y-direction offsets for flexible wiring
✓ Equipped with proteanTecs monitoring technology: A solution capable of real-time monitoring of inter-chiplet connectivity
Copyright © 2026 GUC. All rights reserved.
About GUC
GLOBAL UNICHIP CORP. (GUC) is the Advanced ASIC Leader, leveraging cutting-edge process and packaging technologies to provide the semiconductor industry with world-class IC implementation and SoC manufacturing services. Headquartered in Hsinchu, Taiwan, GUC has built global trust with bases in China, Europe, Japan, Korea, North America, and Vietnam. GUC is publicly traded on the Taiwan Stock Exchange (Ticker: 3443). For more information, please visit our official website (www.guc-asic.com).