AMD Taps Taiwanese OSATs for Fan-Out Advanced Packaging to Seize AI Opportunities

Artificial intelligence (AI) chip giant Advanced Micro Devices (AMD) announced today an investment of over US$10 billion in Taiwan's industrial ecosystem. It will partner with OSAT (Outsourced Semiconductor Assembly and Test) firms including ASE Technology, SPIL, and Powertech Technology (PTI) to develop 2.5D advanced packaging capacity, and cooperate with IC substrate makers like Unimicron, Nan Ya PCB, and Kinsus to accelerate the build-out of AI infrastructure.

Industry analysts note that the supply of TSMC's CoWoS advanced packaging is tight, with most capacity allocated to NVIDIA. This has created an urgent demand for advanced packaging from other AI chip clients, presenting a potential opportunity for Taiwanese OSAT leaders in 2.5D and fan-out panel-level advanced packaging.

In a press release this afternoon, AMD announced its investment of over US$10 billion in Taiwan's industrial ecosystem to meet the demands of AI infrastructure, expanding strategic partnerships to enhance advanced packaging manufacturing capacity for next-generation AI infrastructure.

Within the Elevated Fan-out Bridge (EFB) technology ecosystem, AMD stated it is collaborating with ASE, SPIL, and other partners to jointly develop and validate the next generation of wafer-based 2.5D bridge interconnect technology. AMD also announced a milestone with PTI, successfully validating 2.5D panel-level EFB interconnect technology.

AMD explained that the EFB architecture enhances interconnect bandwidth and improves power efficiency, providing strong support for its Venice central processing units (CPU).

Corporate sources indicate that AMD has long-standing, close collaborations for its processor outsourced packaging and testing orders with ASE and SPIL, both under ASE Technology Holding Co., a partnership that now extends into the realm of AI application processors.

ASE previously stated that its VIPack advanced packaging platform integrates six core packaging technologies, including Fan-Out Package on Package (FOPoP), Fan-Out Chip on Substrate (FOCoS), Fan-Out Chip on Substrate-Bridge (FOCoS-Bridge), Fan-Out System in Package (FOSiP), 2.5D/3D ICs with Through-Silicon Vias (TSV), and co-packaged optics.

SPIL has a long-term focus on Fan-Out Multi-Chip Module (FO-MCM) and Fan-Out Embedded Bridge Multi-Chip Module (FO-EB) packaging technologies. Sources note SPIL's close and long-standing partnership with NVIDIA in High-Performance Computing (HPC) and AI chip back-end packaging.

PTI is optimistic about the application of Fan-Out Panel-Level Packaging (FOPLP) technology in AI chip integration platforms and is actively expanding its FOPLP production lines. At a late-April investor conference, PTI stated it is deepening customer collaboration and accelerating sample validation, with plans for mass production delivery on schedule in 2027.

PTI Chairman D.K. Tsai previously noted that PTI can offer a complete AI chip packaging solution centered on FOPLP advanced packaging. The technology targets AI chips, CPUs, and Application-Specific Integrated Circuits (ASICs), and is also expanding to applications like Optical Engines and Co-Packaged Optics (CPO) with AI chips.