TSMC Leaves Intel, Samsung in the Dust; Mass Produces Largest CoWoS with 98% Yield
At its technology forum, TSMC announced three new advanced processes—A13, A12, and N2U—to pull away from competitors Intel and Samsung. Furthermore, the company revealed it will begin mass production of the world's largest CoWoS this year with a yield rate exceeding 98%.
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- 📰 Published: May 14, 2026 at 16:53
- 🔍 Collected: May 14, 2026 at 17:02 (9 min after Published)
- 🤖 AI Analyzed: May 15, 2026 at 04:09 (11h 7m after Collected)
Central News Agency, Hsinchu, May 14 (Reporter Chang Chien-chung) - Amidst continuous news of Intel and Samsung improving their technology to snatch orders, TSMC not only announced three new advanced processes—A13, A12, and N2U—at its Taiwan Technology Forum today, but also revealed it will mass-produce the world's largest CoWoS this year with a yield rate exceeding 98%. This demonstrates a full commitment to technological leadership and a rapid expansion of advanced process and advanced packaging capacity to support strong customer demand, crushing competitors with its technological lead.
The TSMC Taiwan Technology Forum kicked off today at the Sheraton Hsinchu Hotel. Douglas Hsiao, Senior VP of Worldwide Sales and Co-COO of TSMC, stated that while the growth momentum in semiconductors over the past decade came mainly from mobile phones, the future momentum is expected to come from Artificial Intelligence (AI). He anticipates the global semiconductor market value could reach $1.5 trillion by 2030, with AI and High-Performance Computing (HPC) being the largest contributors at 55%. Michael Juan, Director of Asia Pacific Business, added that TSMC's Asia-Pacific customers used over 2.1 million 12-inch equivalent wafers last year, with a vertical stack height of about 1600 meters, exceeding three Taipei 101 buildings.
Recent reports of breakthroughs by Intel and Samsung in foundry and advanced packaging orders have threatened to break TSMC's global monopoly on advanced technology, making today's technology forum in Taiwan particularly noteworthy. The market is highly focused on TSMC's progress in advanced processes, advanced packaging technology, and capacity expansion.
L.P. Yuan, VP of Business Development at TSMC, stated that TSMC continues to introduce industry-leading technologies and enhance existing platforms to support customer needs. This year, it is launching three advanced processes: A13, A12, and N2U.
He pointed out that the A13 process is an enhanced version of the A14 process, which will allow TSMC to maintain its technological lead in the angstrom era, with mass production expected in 2029. The A12 process will introduce backside power delivery technology to the A14 process platform, achieving better performance, power, and area benefits, also slated for mass production in 2029.
Yuan stated that TSMC's 2-nanometer process entered mass production in the fourth quarter of last year and continues to advance, including N2P, N2X, and the newly introduced N2U. N2P will enter mass production in the second half of this year, with N2X expected in 2028. N2U is a further optimization based on N2P technology, offering better energy efficiency and speed, and will be mass-produced in 2028.
Yuan said that TSMC has received about 25 tape-outs for 2nm products, with over 70 customer designs in planning or progress. The adoption of 2nm is accelerating in AI, HPC, and mobile applications, with the number of tape-outs in the second year of 2nm being about four times that of 5nm in the same period.
Regarding advanced packaging, Yuan stated that TSMC will mass-produce the world's largest 5.5x reticle size CoWoS this year, with a yield rate exceeding 98%. Over the next five years, CoWoS will continue to increase in size annually, integrating more logic and High-Bandwidth Memory (HBM) dies.
Yuan pointed out that TSMC expects to begin producing a 14x reticle size CoWoS integrating 20 HBMs in 2028, and a version integrating 24 HBMs, larger than 14x reticle size, is expected to be ready by 2029.
Po-Jen Tien, VP of Operations at TSMC, said that TSMC's 2nm has entered mass production with a learning curve better than 3nm and will gradually enter people's lives. A16 is on track for mass production in the second half of 2026.
To support customers' growing innovation needs, Tien said TSMC is accelerating fab construction at twice the previous speed and building new fabs globally. In addition, before new capacity comes online, TSMC continues to use digital transformation and AI-driven technologies to increase the output of advanced processes to support urgent customer needs.
Tien noted that TSMC will start five fabs simultaneously in 2026 to rapidly increase 2nm capacity. It is estimated that the 2nm wafer output in the first year will be 45% higher than the 3nm output in the same period, and the compound annual growth rate of 2nm capacity from 2026 to 2028 will reach 70%.
Furthermore, the compound growth rate of TSMC's 3nm and 5nm capacity from 2022 to 2027 will also reach 25%, supporting strong customer demand. Tien said TSMC has overcome geographical limitations to connect its 3nm, 5nm, and 7nm fabs into a Super Giga Fab, using AI to achieve cross-fab optimization and maximize productivity.
Tien stated that the compound growth rate of TSMC's CoWoS and SoIC capacity from 2022 to 2027 will exceed 80%. (Editor: Lin Shu-yuan) 1150514
The TSMC Taiwan Technology Forum kicked off today at the Sheraton Hsinchu Hotel. Douglas Hsiao, Senior VP of Worldwide Sales and Co-COO of TSMC, stated that while the growth momentum in semiconductors over the past decade came mainly from mobile phones, the future momentum is expected to come from Artificial Intelligence (AI). He anticipates the global semiconductor market value could reach $1.5 trillion by 2030, with AI and High-Performance Computing (HPC) being the largest contributors at 55%. Michael Juan, Director of Asia Pacific Business, added that TSMC's Asia-Pacific customers used over 2.1 million 12-inch equivalent wafers last year, with a vertical stack height of about 1600 meters, exceeding three Taipei 101 buildings.
Recent reports of breakthroughs by Intel and Samsung in foundry and advanced packaging orders have threatened to break TSMC's global monopoly on advanced technology, making today's technology forum in Taiwan particularly noteworthy. The market is highly focused on TSMC's progress in advanced processes, advanced packaging technology, and capacity expansion.
L.P. Yuan, VP of Business Development at TSMC, stated that TSMC continues to introduce industry-leading technologies and enhance existing platforms to support customer needs. This year, it is launching three advanced processes: A13, A12, and N2U.
He pointed out that the A13 process is an enhanced version of the A14 process, which will allow TSMC to maintain its technological lead in the angstrom era, with mass production expected in 2029. The A12 process will introduce backside power delivery technology to the A14 process platform, achieving better performance, power, and area benefits, also slated for mass production in 2029.
Yuan stated that TSMC's 2-nanometer process entered mass production in the fourth quarter of last year and continues to advance, including N2P, N2X, and the newly introduced N2U. N2P will enter mass production in the second half of this year, with N2X expected in 2028. N2U is a further optimization based on N2P technology, offering better energy efficiency and speed, and will be mass-produced in 2028.
Yuan said that TSMC has received about 25 tape-outs for 2nm products, with over 70 customer designs in planning or progress. The adoption of 2nm is accelerating in AI, HPC, and mobile applications, with the number of tape-outs in the second year of 2nm being about four times that of 5nm in the same period.
Regarding advanced packaging, Yuan stated that TSMC will mass-produce the world's largest 5.5x reticle size CoWoS this year, with a yield rate exceeding 98%. Over the next five years, CoWoS will continue to increase in size annually, integrating more logic and High-Bandwidth Memory (HBM) dies.
Yuan pointed out that TSMC expects to begin producing a 14x reticle size CoWoS integrating 20 HBMs in 2028, and a version integrating 24 HBMs, larger than 14x reticle size, is expected to be ready by 2029.
Po-Jen Tien, VP of Operations at TSMC, said that TSMC's 2nm has entered mass production with a learning curve better than 3nm and will gradually enter people's lives. A16 is on track for mass production in the second half of 2026.
To support customers' growing innovation needs, Tien said TSMC is accelerating fab construction at twice the previous speed and building new fabs globally. In addition, before new capacity comes online, TSMC continues to use digital transformation and AI-driven technologies to increase the output of advanced processes to support urgent customer needs.
Tien noted that TSMC will start five fabs simultaneously in 2026 to rapidly increase 2nm capacity. It is estimated that the 2nm wafer output in the first year will be 45% higher than the 3nm output in the same period, and the compound annual growth rate of 2nm capacity from 2026 to 2028 will reach 70%.
Furthermore, the compound growth rate of TSMC's 3nm and 5nm capacity from 2022 to 2027 will also reach 25%, supporting strong customer demand. Tien said TSMC has overcome geographical limitations to connect its 3nm, 5nm, and 7nm fabs into a Super Giga Fab, using AI to achieve cross-fab optimization and maximize productivity.
Tien stated that the compound growth rate of TSMC's CoWoS and SoIC capacity from 2022 to 2027 will exceed 80%. (Editor: Lin Shu-yuan) 1150514