TSMC North America Technology Symposium debuts, introduces A13 process for 2029 production
TSMC unveiled its A13 process technology at the North America Technology Symposium, targeting 2029 production for AI and HPC. It also revealed roadmaps for advanced packaging and silicon photonics.
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- 📰 Published: April 23, 2026 at 09:53
- 🔍 Collected: April 23, 2026 at 10:01 (7 min after Published)
- 🤖 AI Analyzed: April 23, 2026 at 11:58 (1h 57m after Collected)
Central News
(CNA, Hsinchu, 23rd) Foundry TSMC held its North America Technology Symposium on the 22nd (US time), debuting its newly developed A13 process technology to meet customer demand for next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications, with production expected in 2029.
TSMC's North America Technology Symposium was held in Santa Clara, California, with the theme "Leading Silicon Technology Accelerates Artificial Intelligence." It is TSMC's largest customer event of the year, revealing the latest technological developments and manufacturing services.
TSMC Chairman and CEO C.C. Wei stated via a press release that TSMC's customers always focus on future innovations and expect TSMC to continuously provide reliable new technologies, such as the A13 process. He emphasized that these technologies will be ready and in mass production just in time when customers' forward-looking new designs require them.
Wei said TSMC's advanced process technologies lead the industry in density, performance, and power efficiency. The company continues to find ways to optimize them to better support customers' future products, ensuring their success as their most reliable technology partner.
TSMC pointed out that the A13 process technology is one of the key technological innovations announced at the symposium. Compared to the A14 process, A13 saves 6% of the area and is completely compatible with A14 design rules, allowing customers to quickly upgrade their designs to TSMC's latest nanosheet transistor technology. Additionally, through design and technology co-optimization, A13 provides extra power efficiency and performance improvements, with production slated for 2029.
In advanced logic technology, TSMC also previewed the A12 process, which will adopt TSMC's Super Power Rail technology to provide backside power delivery for AI and HPC applications, expected for production in 2029.
TSMC is also advancing its 2nm platform with the N2U technology, utilizing design and technology co-optimization to boost speed by 3% to 4% over N2P, or reduce power consumption by 8% to 10%, while increasing logic density by 2% to 3%. N2U supports AI, HPC, and mobile applications, with production expected to begin in 2028.
Regarding advanced packaging and 3D silicon stacking, TSMC is producing CoWoS at 5.5 times the reticle size and planning a larger CoWoS at 14 times the reticle size, capable of integrating about 10 large compute dies and 20 high-bandwidth memory (HBM) stacks, expected to start production in 2028. By 2029, TSMC expects to introduce CoWoS larger than 14 times the reticle size and a System-on-Wafer (SoW-X) technology at 40 times the reticle size.
TSMC also launched the System-on-Integrated-Chips (SoIC) 3D chip stacking technology under its advanced technology platform. A14-on-A14 SoIC is expected to be produced in 2029, offering a die-to-die I/O density 1.8 times higher than that of 2nm-on-2nm SoIC, supporting higher data transfer bandwidths.
TSMC noted that its Compact Universal Photonic Engine (COUPE) will reach a crucial milestone, with the true co-packaged optics (CPO) solution using COUPE on substrate expected to begin production in 2026. Compared to pluggable solutions on circuit boards, it provides double the power efficiency and reduces latency by 90%. It is already applied to 200Gbps micro-ring modulators (MRMs) as a solution for data transmission between data center racks.
To meet the needs of automotive and edge AI applications, TSMC launched the N2A process technology, the first automotive process using nanosheet transistors. Compared to N3A, N2A will boost speeds by 15% to 20% at the same power consumption and is expected to complete AEC-Q100 validation in 2028.
Furthermore, TSMC offers automotive design kits within its N2P Process Design Kit (PDK), allowing customers to factor automotive operating conditions into their designs and start designing early, pending full validation of the N2A process.
In specialty technologies, TSMC will introduce high-voltage technology to the FinFET generation in 2026. The N16HV process primarily supports display driver applications. For smartphone display drivers, N16HV increases gate density by 41% and reduces power by 35% compared to the N28HV process. For near-eye displays, N16HV shrinks chip area by 40% and cuts power consumption by over 20%, enhancing the usability of applications like smart glasses. (Editor: Zhang Junmao) 1150423
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(CNA, Hsinchu, 23rd) Foundry TSMC held its North America Technology Symposium on the 22nd (US time), debuting its newly developed A13 process technology to meet customer demand for next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications, with production expected in 2029.
TSMC's North America Technology Symposium was held in Santa Clara, California, with the theme "Leading Silicon Technology Accelerates Artificial Intelligence." It is TSMC's largest customer event of the year, revealing the latest technological developments and manufacturing services.
TSMC Chairman and CEO C.C. Wei stated via a press release that TSMC's customers always focus on future innovations and expect TSMC to continuously provide reliable new technologies, such as the A13 process. He emphasized that these technologies will be ready and in mass production just in time when customers' forward-looking new designs require them.
Wei said TSMC's advanced process technologies lead the industry in density, performance, and power efficiency. The company continues to find ways to optimize them to better support customers' future products, ensuring their success as their most reliable technology partner.
TSMC pointed out that the A13 process technology is one of the key technological innovations announced at the symposium. Compared to the A14 process, A13 saves 6% of the area and is completely compatible with A14 design rules, allowing customers to quickly upgrade their designs to TSMC's latest nanosheet transistor technology. Additionally, through design and technology co-optimization, A13 provides extra power efficiency and performance improvements, with production slated for 2029.
In advanced logic technology, TSMC also previewed the A12 process, which will adopt TSMC's Super Power Rail technology to provide backside power delivery for AI and HPC applications, expected for production in 2029.
TSMC is also advancing its 2nm platform with the N2U technology, utilizing design and technology co-optimization to boost speed by 3% to 4% over N2P, or reduce power consumption by 8% to 10%, while increasing logic density by 2% to 3%. N2U supports AI, HPC, and mobile applications, with production expected to begin in 2028.
Regarding advanced packaging and 3D silicon stacking, TSMC is producing CoWoS at 5.5 times the reticle size and planning a larger CoWoS at 14 times the reticle size, capable of integrating about 10 large compute dies and 20 high-bandwidth memory (HBM) stacks, expected to start production in 2028. By 2029, TSMC expects to introduce CoWoS larger than 14 times the reticle size and a System-on-Wafer (SoW-X) technology at 40 times the reticle size.
TSMC also launched the System-on-Integrated-Chips (SoIC) 3D chip stacking technology under its advanced technology platform. A14-on-A14 SoIC is expected to be produced in 2029, offering a die-to-die I/O density 1.8 times higher than that of 2nm-on-2nm SoIC, supporting higher data transfer bandwidths.
TSMC noted that its Compact Universal Photonic Engine (COUPE) will reach a crucial milestone, with the true co-packaged optics (CPO) solution using COUPE on substrate expected to begin production in 2026. Compared to pluggable solutions on circuit boards, it provides double the power efficiency and reduces latency by 90%. It is already applied to 200Gbps micro-ring modulators (MRMs) as a solution for data transmission between data center racks.
To meet the needs of automotive and edge AI applications, TSMC launched the N2A process technology, the first automotive process using nanosheet transistors. Compared to N3A, N2A will boost speeds by 15% to 20% at the same power consumption and is expected to complete AEC-Q100 validation in 2028.
Furthermore, TSMC offers automotive design kits within its N2P Process Design Kit (PDK), allowing customers to factor automotive operating conditions into their designs and start designing early, pending full validation of the N2A process.
In specialty technologies, TSMC will introduce high-voltage technology to the FinFET generation in 2026. The N16HV process primarily supports display driver applications. For smartphone display drivers, N16HV increases gate density by 41% and reduces power by 35% compared to the N28HV process. For near-eye displays, N16HV shrinks chip area by 40% and cuts power consumption by over 20%, enhancing the usability of applications like smart glasses. (Editor: Zhang Junmao) 1150423
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The text, images, and audio/video on this website may not be reproduced, publicly broadcast, or publicly transmitted and utilized without authorization.