KYEC Expands Capital Expenditure to Record NT$50 Billion; Strong Demand for AI Testing
To address the surging complexity and longer testing times of advanced AI chips and CoWoS packaging, KYEC has significantly increased its 2026 capital expenditure to a record NT$50 billion.
📋 Article Processing Timeline
- 📰 Published: April 10, 2026 at 16:36
- 🔍 Collected: April 10, 2026 at 17:00 (24 min after Published)
- 🤖 AI Analyzed: April 20, 2026 at 06:46 (229h 46m after Collected)
King Yuan Electronics (KYEC) announced at the end of December 2025 a capital expenditure of NT$39.372 billion for 2026, surpassing the NT$37 billion scale of 2025. Today, the company announced a further increase in its capital expenditure to NT$50 billion, continuously breaking company records. KYEC noted the specific purpose is to meet operational needs for capacity expansion.
Institutional investors estimate that KYEC will expand its capacity by 30% to 50% this year, aggressively expanding its high-power burn-in testing capacity in particular.
Industry analysts point out that wafer processes for artificial intelligence (AI) processors or related application-specific integrated circuits (ASICs) are comprehensively shrinking to the 3-nanometer or even 2-nanometer generations. Coupled with advanced packaging like CoWoS, chip density is greatly increasing, power consumption is rising, and heterogeneous chip integration has become the mainstream. Under these conditions, error tolerance is becoming increasingly strict, significantly elevating the importance of the testing process. The duration for wafer testing and final product testing is extending, and complexity is increasing. This forces KYEC to raise its capital expenditure and expand testing capacity to meet the robust demand from AI chip clients.
Investors noted that in 2025, AI-related testing accounted for over 25% of KYEC's total revenue. It is expected that the proportion of AI testing revenue will exceed 30% this year. KYEC continues to benefit from the momentum of final product testing for major clients' high-end AI chip platforms and the demand for ASIC high-power burn-in testing. (Editor: Zhai Si-jia) 1150410
Institutional investors estimate that KYEC will expand its capacity by 30% to 50% this year, aggressively expanding its high-power burn-in testing capacity in particular.
Industry analysts point out that wafer processes for artificial intelligence (AI) processors or related application-specific integrated circuits (ASICs) are comprehensively shrinking to the 3-nanometer or even 2-nanometer generations. Coupled with advanced packaging like CoWoS, chip density is greatly increasing, power consumption is rising, and heterogeneous chip integration has become the mainstream. Under these conditions, error tolerance is becoming increasingly strict, significantly elevating the importance of the testing process. The duration for wafer testing and final product testing is extending, and complexity is increasing. This forces KYEC to raise its capital expenditure and expand testing capacity to meet the robust demand from AI chip clients.
Investors noted that in 2025, AI-related testing accounted for over 25% of KYEC's total revenue. It is expected that the proportion of AI testing revenue will exceed 30% this year. KYEC continues to benefit from the momentum of final product testing for major clients' high-end AI chip platforms and the demand for ASIC high-power burn-in testing. (Editor: Zhai Si-jia) 1150410