Intel Foundry Announces Process Advancements and Future Innovations at VLSI Symposium

Intel Foundry has announced the latest updates on its process roadmap and long-term innovation investments at the 2026 VLSI Symposium. The company revealed that Intel 18A-P, the first performance-enhanced variant in the Intel 18A family, has entered risk production. This marks progress in line with the schedule previously shared with customers and partners.

Naga Chandrasekaran, Senior Vice President and General Manager of Intel Foundry at Intel Corporation, said, "The updates and announcements at VLSI demonstrate Intel Foundry’s ongoing commitment to pioneering advancements in process technology for our customers and partners. This is a long journey, and our work continues, but we are pleased to share progress on Intel 18A-P and our long-term R&D efforts."

Latest Intel 18A-P Updates Announced at VLSI

Intel Foundry is achieving performance, power efficiency, and design advantages in Intel 18A-P by combining transistor, interconnect, and design-technology co-optimization. At VLSI, Intel Foundry engineers detailed the following advanced technologies:

- Intel 18A-P achieves a 9% performance gain at iso-power or an 18% reduction in power consumption at iso-performance compared to Intel 18A, while also improving thermal characteristics and design flexibility - The new transistor option 'Power Boost' in Intel 18A-P enables a low-resistance dual-contact structure, increasing drive current and operating frequency at the same capacitance - Thermal resistance is reduced by 20–40% through innovations in both materials and design - Via resistance (vertical interconnects between chip layers) is improved by 10–30% through shape and material optimization - Strain engineering enhances PMOS mobility, improving current flow efficiency within transistors - New transistor options for both low-power and high-performance applications - A fifth logic Vt pair option added between ULVT and LVT, enabling designers to fine-tune the balance between speed and power - Intel 18A-P maintains full design rule compatibility with Intel 18A, enabling easy reuse of existing IP and design flows - Intel 18A-P offers two cell heights (180nm and 160nm) and a 50nm contacted poly pitch, same as Intel 18A

Additional Updates Announced at VLSI

Last year, Intel Foundry introduced Gate-All-Around (GAA) transistors and Backside Power Delivery (BSPD) technology to market using the Intel 18A process. This week, the company’s technical team discussed how these technologies contribute to improved performance, power efficiency, and scaling in future logic designs.

During a VLSI keynote, Eric Karl, Vice President and Fellow at Intel Foundry, quantified the advantages of backside power delivery and GAA transistors. Karl stated that by reducing routing area by 11% and dynamic voltage drop by 10x, these technologies enable up to a 6% frequency increase or over 15% reduction in dynamic power consumption compared to equivalent surface interconnect technologies.

Manju Shamanna from Intel Foundry’s Silicon & Platform Engineering group presented real silicon measurement results from CPU cores manufactured using GAA and backside power delivery processes. His research demonstrated stronger frequency scaling at lower voltages—including approximately 30% higher frequency at low voltage (~0.5V)—while achieving more efficient operation due to reduced IR drop (voltage drop).

Future Innovations Highlighted at VLSI

Intel Foundry also shared updates on long-term research spanning multiple areas critical to future silicon scaling:

- CFET (Complementary FET): Intel demonstrated a monolithic CFET inverter with vertically stacked NMOS and PMOS devices at a 45nm gate pitch. The vertical stacking architecture paves the way for continued logic scaling beyond GAA transistors - Integration of 'GaN (Gallium Nitride) + Si (Silicon)' for power management: Intel demonstrated integrating GaN power devices with silicon logic containing approximately 1,000 gates of digital control circuitry on a single chip on 300mm wafers. This enables coexistence of high-efficiency, large-scale digital control and high-performance power devices within the same process without increasing system complexity - Subtractive Ruthenium Interconnect: Intel demonstrated a subtractive ruthenium interconnect with integrated air gaps. Compared to traditional copper interconnects, it achieves up to ~35% reduction in capacitance and measurable frequency improvement. As interconnects scale down, this is an effective approach to improve resistance-capacitance (RC) scaling